DocumentCode :
3548495
Title :
Some practical issues in the design of fault-tolerant multiprocessors
Author :
Dutt, S. ; Hayes, J.P.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
1991
fDate :
25-27 June 1991
Firstpage :
292
Lastpage :
299
Abstract :
A node-covering approach to fault-tolerant design is generalized to apply to a wide class of multiprocessor structures whose structure and failure mechanisms are represented by arbitrary graphs. Several new types of covering graphs are defined, which lead to various design tradeoffs. A new technique for incremental design, using a class of switch implementations that reduce a system´s interconnection costs, is presented. The reduction of other cost factors is addressed, including VLSI layout area minimization, efficient transfer of state information during recovery, and the efficient use of local spares. A fast and distributed algorithm for reconfiguration around faults is presented. A review of the general node covering theory is included, focusing on how it models the important practical features of fault-tolerant systems.<>
Keywords :
computational complexity; fault tolerant computing; graph theory; multiprocessing systems; VLSI layout area minimization; covering graphs; distributed algorithm; failure mechanisms; fault-tolerant design; incremental design; local spares; multiprocessor structures; node-covering; state information; switch implementations; Computer architecture; Costs; Distributed algorithms; Fault tolerance; Fault tolerant systems; Large-scale systems; Military computing; Multiprocessing systems; Switches; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium
Conference_Location :
Montreal, Quebec, Canada
Print_ISBN :
0-8186-2150-8
Type :
conf
DOI :
10.1109/FTCS.1991.146676
Filename :
146676
Link To Document :
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