• DocumentCode
    3549282
  • Title

    An improved unified scalable radix-2 Montgomery multiplier

  • Author

    Harris, David ; Krishnamurthy, Ram ; Anders, Mark ; Mathew, Sanu ; Hsu, Steven

  • Author_Institution
    Harvey Mudd Coll., Claremont, CA, USA
  • fYear
    2005
  • fDate
    27-29 June 2005
  • Firstpage
    172
  • Lastpage
    178
  • Abstract
    This paper describes an improved version of the Tenca-Koc unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement. Like the Tenca-Koc multiplier, this design is reconfigurable to accept any input precision in either GF(p) or GF(2n) up to the size of the on-chip memory. An FPGA implementation can perform 1024-bit modular exponentiation in 16 ms using 5598 4-input lookup tables, making it the fastest unified scalable design yet reported.
  • Keywords
    Galois fields; cryptography; digital arithmetic; field programmable gate arrays; multiplying circuits; system-on-chip; table lookup; FPGA implementation; Tenca-Koc multiplier; lookup table; on-chip memory; radix-2 Montgomery multiplier; Circuits; Delay; Educational institutions; Elliptic curve cryptography; Field programmable gate arrays; Galois fields; Hardware; Laboratories; Polynomials; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic, 2005. ARITH-17 2005. 17th IEEE Symposium on
  • ISSN
    1063-6889
  • Print_ISBN
    0-7695-2366-8
  • Type

    conf

  • DOI
    10.1109/ARITH.2005.9
  • Filename
    1467637
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549282