How effective are failure analysis methods for the 65nm CMOS technology node?

Various 65 nm CMOS technology FA case studies have been presented and it is concluded that to maintain a high FA success rate for <65nm technologies it is necessary to: (1) improve the characteristics of existing tools considerably: immersion lenses and lock-in amplifiers to improve spatial resolution and detection sensitivity of laser stimulation methods were tested. For SEM imaging, newest generation, high resolution columns exhibiting significantly better performances at low electron beam energies (< 1kV) are now in use; and (2) develop new fault isolation methods (Seebeck imaging, Electro-plating localization, RCI) to also cover the most difficult failure analyses of e.g. high resistive structures.