Title :
Application of logic mapping in the low voltage functional failure analysis
Author :
Ho, Eng Keong ; Lee, Meng Khuan
Author_Institution :
Syst. on Silicon Manuf. Co., Singapore, Singapore
fDate :
27 June-1 July 2005
Abstract :
Logic mapping is shown to be a good debug technique to increase the PFA success rate in logic failures, especially low voltage functional failures. The faster cycle time in PFA is especially critical in today fast product yield ramp up. The results from this paper demonstrated that logic mapping is capable of isolating hard defects, which cause functional failures at all voltages in advance CMOS devices. Furthermore, we demonstrated that logic mapping is also capable of isolating VLV related failures as well.
Keywords :
CMOS logic circuits; failure analysis; logic testing; advance CMOS devices; debug technique; hard defects isolation; logic failures; logic mapping; low voltage functional failures; physical failure analysis; product yield; very low voltage testing; Circuit faults; Circuit testing; Failure analysis; Logic design; Logic devices; Logic testing; Low voltage; Manufacturing; Silicon; Temperature;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
DOI :
10.1109/IPFA.2005.1469128
