Interfacial stress characterization for stress-induced voiding in Cu/low-k interconnects

Author

Wang, Robin C J ; Chen, L.D. ; Yen, P.C. ; Lin, S.R. ; Chiu, C.C. ; Wu, Kenneth ; Chang-Liao, K.S.

Author_Institution

Dept. of Eng. & Syst. Sci., Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan

fYear

2005

fDate

27 June-1 July 2005

Firstpage

96

Lastpage

99

Abstract

Stress-induced voiding (SIV) was studied in the aspects of global and localized stress variation with the change of copper geometries. Two types of interconnect structures were adopted to evaluate resistance shift versus bake time and feature size effect in Cu/low-k systems. A 3D modeling of finite element analysis (FEA) was conducted to profile the stress contour, which directly attributed to the copper voiding underneath via as well as inside via.

Keywords

copper; finite element analysis; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; stress effects; voids (solid); BEOL reliability; Cu; Cu interconnects; copper voiding; finite element analysis; hydrostatics stress; interconnect structure; interfacial stress; resistance shift; stress contour; stress migration; stress-induced voiding; Copper; Dielectrics; Failure analysis; Finite element methods; Geometry; Integrated circuit interconnections; Semiconductor device manufacture; Temperature; Testing; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the

Print_ISBN

0-7803-9301-5

Type

conf

DOI

10.1109/IPFA.2005.1469138

Filename

1469138