Controlling injected electron and hole profiles for better reliability of split gate SONOS

Author

Sridhar, K. ; Kumar, P. Bharath ; Mahapatra, S. ; Murakami, E. ; Kamohara, S.

Author_Institution

Indian Inst. of Technol., Mumbai, India

fYear

2005

fDate

27 June-1 July 2005

Firstpage

190

Lastpage

194

Abstract

SONOS memory cell using a split gate structure is studied using simulations. The dependence of channel hot electron (HE) and hot hole (HH) profiles (during program and erase) on bias, doping, and program gate length (L_PG) is studied. The effect of trapped charge position on the threshold voltage is also studied. L_PG is found to be crucial in minimizing the mismatch of HE and HH profiles as the regions of their generation are separate. Program gate voltage during program and erase is found to be the key bias for spatially adjusting the HE and HH profiles.

Keywords

electron traps; hole traps; hot carriers; integrated circuit reliability; integrated memory circuits; network analysis; SONOS memory cell; channel hot electron; hot hole profiles; injected electron controlling; program gate length; program gate voltage; reliability; split gate structure; threshold voltage; trapped charge position; Channel hot electron injection; Charge carrier processes; Computational modeling; Doping profiles; Electron traps; Helium; Hot carriers; MOSFETs; SONOS devices; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the

Print_ISBN

0-7803-9301-5

Type

conf

DOI

10.1109/IPFA.2005.1469159

Filename

1469159