Challenges in barrier and seed layers characterization of copper technology IC devices

Author

Li, K. ; Er, E. ; Yeow, T. ; Tang, D.

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

2005

fDate

27 June-1 July 2005

Firstpage

263

Lastpage

266

Abstract

Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 μm and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.

Keywords

copper; integrated circuit metallisation; materials preparation; tantalum; transmission electron microscopy; 0.13 micron; 90 nm; Cu; TEM imaging; Ta; barrier characterization; copper technology IC devices; integrated circuit metallisation; sample preparation; seed layer characterization; transmission electron microscopy; Copper; Electrons; Erbium; Integrated circuit technology; Manufacturing industries; Metals industry; Pulp manufacturing; Semiconductor device manufacture; Tunneling; Wood industry;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the

Print_ISBN

0-7803-9301-5

Type

conf

DOI

10.1109/IPFA.2005.1469175

Filename

1469175

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549749