Title :
A study of defects causing yield loss in copper backend process due to the power shorts
Author :
Kamat, Nitin R. ; Lal, Manni ; Khiam, Oh Chong
Author_Institution :
Chartered Semicond. Manuf. Ltd., Singapore
fDate :
27 June-1 July 2005
Abstract :
In this paper an attempt is made to understand and explain the fundamental challenges involved in integrating copper as interconnect scheme with the dual damascene approach. Most basic electrical failure mode like the power shorts is discussed and the impact to the yield of the product is investigated. Although, the most basic type of failure in a device, power shorts in many cases, could be the most prominent yield limiting factor. Different types of processing anomalies that could result in power shorts, many, very unique to devices with copper back-end scheme are discussed.
Keywords :
chemical mechanical polishing; chemical vapour deposition; copper; electrical faults; electroplating; etching; integrated circuit interconnections; integrated circuit yield; chemical mechanical polishing; chemical vapour deposition; copper backend process; copper integration; electrical failure mode; electrical faults; electroplating; etching; integrated circuit interconnections; integrated circuit yield; power shorts; yield loss; Aluminum; Bonding; Conductivity; Copper; Dielectric constant; Etching; Polyimides; Pulp manufacturing; Semiconductor device manufacture; Testing;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
DOI :
10.1109/IPFA.2005.1469177
