DocumentCode :
3549755
Title :
Couple passive voltage contrast with scanning probe microscope to identify invisible defect out
Author :
Shen, Cha-Ming ; Chou, Jing-Hong
Author_Institution :
Taiwan Semicond. Manuf. Co. Ltd., Tainan, Taiwan
fYear :
2005
fDate :
27 June-1 July 2005
Firstpage :
290
Lastpage :
293
Abstract :
As most of us know, PVC (passive voltage contrast) is a popular technique used to determine open or short issue on failure analysis field as presented in T. Sakai et al. (1999). And SPM (scanning probe microscopy) is another powerful technique for measuring characterization of dielectric or judging gate-oxide integrity of device as stated in M. P. Murell et al. (1993). In this paper, a judicious and effective ratiocinating method that coupled PVC with SPM would be discussed for revealing some special invisible defect modes, which were imperceptible to observe and very difficult to identify out by means of traditional PFA skills. And two such examples, whose failure position could not be caught exactly not only for the most sensitive PVC but high-resolution current mapping of SPM, would be presented to certify the benefit and excellence of this ratiocinating method. After our experiment, to apply such ratiocinating method could provide a good thinking in profile and help to reason the fault model. Simultaneously, the specific failure mechanism and defect location could be deduced before the conclusive PFA. Thus failure analysis turn-around time would not be wasted and yield-improving strategy could be proposed as soon as possible. So the application is successful.
Keywords :
failure analysis; integrated circuit testing; integrated circuit yield; scanning probe microscopy; defect location; dielectric characterization; failure analysis; failure mechanism; fault model; gate-oxide integrity; high-resolution current mapping; invisible defect modes; passive voltage contrast; ratiocinating method; scanning probe microscope; yield-improving strategy; Dielectric devices; Dielectric measurements; Electron emission; Failure analysis; Integrated circuit technology; Scanning electron microscopy; Scanning probe microscopy; Semiconductor device manufacture; Surface topography; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN :
0-7803-9301-5
Type :
conf
DOI :
10.1109/IPFA.2005.1469181
Filename :
1469181
Link To Document :
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