Layout impact on the performance of a locally strained PMOSFET

Author

Eneman, Geert ; Verheyen, P. ; Rooyackers, R. ; Nouri, F. ; Washington, L. ; Degraeve, R. ; Kaczer, B. ; Moroz, V. ; De Keersgieter, An ; Schreutelkamp, R. ; Kawaguchi, M. ; Kim, Y. ; Samoilov, A. ; Smith, L. ; Absil, P.P. ; De Meyer, K. ; Jurczak, M. ; B

fYear

2005

fDate

14-16 June 2005

Firstpage

22

Lastpage

23

Abstract

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L_sd/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.

Keywords

Ge-Si alloys; MOSFET; semiconductor device reliability; 45 nm; NBTI; S-D PMOSFET technology; SiGe; TDDB; gate length transistors; layout dependence; oxide reliability; source-drain length; Compressive stress; Current measurement; Degradation; Etching; Germanium silicon alloys; Length measurement; MOSFET circuits; Niobium compounds; Silicon germanium; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469196

Filename

1469196