Title :
S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond
Author :
Kim, J.-Y. ; Oh, H.J. ; Woo, D.S. ; Lee, Y.S. ; Kim, D.H. ; Kim, S.E. ; Ha, G.W. ; Kim, H.J. ; Kang, N.J. ; Park, J.M. ; Hwang, Y.S. ; Kim, D.I. ; Park, B.J. ; Huh, M. ; Lee, B.H. ; Kim, S.B. ; Cho, M.H. ; Jung, M.Y. ; Kim, Y.J. ; Jin, C. ; Shin, D.W. ; S
Author_Institution :
Adv. Technol. Dev. Semicond. R&D Div., Samsung Electron. Co., Yongin, South Korea
Abstract :
For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.
Keywords :
DRAM chips; insulated gate field effect transistors; leakage currents; mobile communication; nanopatterning; semiconductor junctions; 2 Gbit; 50 nm; 70 nm; DIBL; DRAM; S-RCAT; body effect; data retention time; junction leakage current; mobile application; recessed-channel structure; sphere-shaped-recess-channel-array transistor; subthreshold swing; Computer aided engineering; Neck; Paper technology; Random access memory; Research and development; Transistors; Very large scale integration;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469201
