Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

Author

Ranica, R. ; Villaret, A. ; Malinge, P. ; Gasiot, G. ; Mazoyer, P. ; Roche, P. ; Candelier, P. ; Jacquet, F. ; Masson, P. ; Bouchakour, R. ; Fournel, R. ; Schoellkopf, J.P. ; Skotnicki, T.

Author_Institution

STMicroelectron., Crolles, France

fYear

2005

fDate

14-16 June 2005

Firstpage

38

Lastpage

39

Abstract

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

Keywords

CMOS integrated circuits; DRAM chips; nanotechnology; system-on-chip; 90 nm; CMOS 90nm technology; IT cell; bulk substrate; embedded memory; gate length; gate oxide thickness; high density eDRAM; logic process integration; low-cost eDRAM applications; memory effect amplitude; retention time; scaled IT-Bulk devices; transistor DRAM cell; CMOS logic circuits; CMOS process; CMOS technology; Error analysis; Fabrication; Impact ionization; Logic devices; Logic programming; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469203

Filename

1469203