DocumentCode
3549789
Title
Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlOx(N) CMOSFETs
Author
Kadoshima, M. ; Ogawa, A. ; Takahashi, M. ; Ota, H. ; Mise, N. ; Iwamoto, K. ; Migita, S. ; Fujiwara, H. ; Satake, H. ; Nabatame, T. ; Toriumi, A.
Author_Institution
MIRAI-ASET, Tsukuba, Japan
fYear
2005
fDate
14-16 June 2005
Firstpage
70
Lastpage
71
Abstract
Threshold voltage (Vth) tuning by controlling Fermi-level pinning (FLP) position on HfAlOx(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlOx(N) to modulate the FLP position. The other is the doping into the PtSix<1.0 (partial silicide: PASI) gates on HfAlOx(N) dielectrics. Symmetrical Vth values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlOx(N).
Keywords
CMOS integrated circuits; Fermi level; MIS structures; MOSFET; aluminium compounds; annealing; dielectric materials; hafnium compounds; semiconductor doping; work function; AI compositional modulation; Al concentration control; CMOSFET; FUSI-NiSi gate; Fermi level pinning; HfAlOx-PtSi-Ni; PASI; Vth value; doped partial silicide; doping; foil silicide; high-k dielectrics; n-MOSFET; p-MOSFET; poly-Si gate; threshold voltage tuning; work function tuning; Annealing; CMOSFETs; Doping; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; MOSFETs; Silicides; Threshold voltage; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-00-1
Type
conf
DOI
10.1109/.2005.1469216
Filename
1469216
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