Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni₃Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V_t control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V_t shifts - at higher thermal budgets. We show that V_t and WF shifts are larger on high-K (HfO₂ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni₃Si FUSI, with no phase control issues, and report HfSiON Ni₃Si FUSI PMOS devices with V_t= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.