Author :
Witters, L. ; Collaert, N. ; Nackaerts, A. ; Demand, M. ; Demuynek, S. ; Delvaux, C. ; Lauwers, A. ; Baerts, C. ; Beckx, S. ; Bouilart, W. ; Brus, S. ; Degroote, B. ; De Marneffe, J.F. ; Dixit, A. ; Meyer, K. De ; Ercken, M. ; Goodwin, M. ; Hendrickx, E.
Abstract :
We present the fabrication process of a fully functional 0.274μm2 6T-SRAM cell with inserted-TaxNy tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274μm2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.
Keywords :
CMOS logic circuits; SRAM chips; circuit noise; circuit optimisation; tantalum compounds; CMOS logic circuit; SRAM cell; TaxNy; litho process optimization; static noise margin; tall triple-gate device; CMOS logic circuits; Fabrication; Instruments; Layout; Lighting; Logic circuits; Logic devices; Noise reduction; Random access memory; Size control;
