Author :
Boeuf, F. ; Arnaud, F. ; Boccaccio, C. ; Salvetti, F. ; Todeschini, J. ; Pain, L. ; Jurdit, M. ; Manakli, S. ; Icard, B. ; Planes, N. ; Gierczynski, N. ; Denorme, S. ; Borot, B. ; Ortolland, C. ; Duriez, B. ; Tavel, B. ; Gouraud, P. ; Broekaart, M. ; DeJo
Abstract :
This work highlights the realization and 0.248μm2 to 0.334μm2 SRAM bit-cells with conventional bulk technology based on 19Å CET SiON gate oxide, poly-silicon gate electrode, and mobility enhancement techniques for both nMOS and pMOS. High density critical lithography levels have been exposed with e-beam direct writing thus contributing to the overall cost-effectiveness of the technology.
Keywords :
MOS integrated circuits; SRAM chips; carrier mobility; electron beam lithography; silicon compounds; 6T-SRAM bit-cells; CET SiON gate oxide; SiON; conventional bulk technology; e-beam direct writing; high density critical lithography; mobility enhancement techniques; nMOS; pMOS; poly-silicon gate electrode; CMOS technology; Contacts; Costs; Electrodes; Energy management; Lithography; MOS devices; Pain; Random access memory; Technology management;
