Title :
Advantages of gate work-function engineering by incorporating sub-monolayer Hf at SiON/poly-Si interface in low-power CMOS
Author :
Shimamoto, Y. ; Yugami, J. ; Inoue, M. ; Mizutani, M. ; Hayashi, T. ; Shiga, K. ; Fujita, F. ; Yoneda, M. ; Matsuoka, H.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
The impact of gate work-function (WF) engineering on low-power devices is investigated by incorporating sub-monolayer Hf at SiON/poly-Si interface. An increase of threshold voltage (VT) by WF control allows the use of lower substrate impurity concentrations. This leads to significant increase of carrier mobility and thus ION. Moreover, the gate leakage current is reduced by WF control due to the decrease of oxide field or the increase of barrier height. We successfully demonstrate improvement of 16 % (nFET) and 5 % (pFET) in ION for 65-nm LOP devices when Vdd = 0.9 V.
Keywords :
CMOS integrated circuits; carrier mobility; field effect transistors; hafnium; leakage currents; low-power electronics; semiconductor-insulator boundaries; silicon compounds; work function; 0.9 V; 65 nm; Fermi-level pinning; LOP devices; SiON/poly-Si interface; WF control; carrier mobility; gate leakage current; gate work-function engineering; low-power CMOS; nFET; pFET; sub-monolayer Hf; threshold voltage; Channel bank filters; Dielectric substrates; Electron mobility; Gate leakage; Hafnium; High-K gate dielectrics; Impurities; Laboratories; Maintenance engineering; Threshold voltage;
Conference_Titel :
VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-00-1
DOI :
10.1109/.2005.1469241
