Author :
Ota, K. ; Yokoyama, T. ; Kawasaki, H. ; Moriya, M. ; Kanai, T. ; Takahashi, S. ; Sanuki, T. ; Hasumi, E. ; Komoguchi, T. ; Sogo, Y. ; Takasu, Y. ; Eda, E. ; Oishi, A. ; Kasai, K. ; Ohno, K. ; Iwai, M. ; Saito, M. ; Matsuoka, F. ; Nagashima, N. ; Noguchi,
Author_Institution :
Semicond. Solutions Network Co., Sony Corp., Kanagawa, Japan
Abstract :
The most suitable STI filling process has been developed for 45nm-node SoC platform. We found that the stress induced anti-isotropic impurity diffusion, which causes the Vth lowering. This novel phenomenon has been controlled by optimizing the SOD/HDP-CVD hybrid STI filling structure. At the same time, 20% drive current improvements of nFET and pFET have been obtained.
Keywords :
MOSFET; chemical vapour deposition; circuit optimisation; field effect transistors; filling; hybrid integrated circuits; isolation technology; system-on-chip; 45nm-node SoC platform; CMOSFETs; SOD/HDP-CVD hybrid STI filling structure; STI filling process; Vth lowering; anti-isotropic impurity diffusion; nFET; pFET; shallow trench isolation technology; CMOSFETs; Impurities; Isolation technology; Paper technology; Stress control; Very large scale integration;
