CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Author

Anil, K.G. ; Verheyen, P. ; Collaert, N. ; Dixit, A. ; Kaczer, B. ; Snow, J. ; Vos, R. ; Locorotondo, S. ; Degroote, B. ; Shi, X. ; Rooyackers, R. ; Mannaert, G. ; Brus, S. ; Yim, Y.S. ; Lauwers, A. ; Goodwin, M. ; Kittl, J.A. ; van Dal, M. ; Richard, O.

Author_Institution

Interuniv. Microelectron. Center, Leuven, Belgium

fYear

2005

fDate

14-16 June 2005

Firstpage

198

Lastpage

199

Abstract

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V_T of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I_on-I_off of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V_D=l .3V for an EOT of 1.8nm.

Keywords

MOSFET; chemical mechanical polishing; masks; silicon-on-insulator; 0.18 V; 1.0 to 0.2 V; 50 nm; CMP-less dual hard mask scheme; CMP-less integration; FinFET; NFET; Ni; PFET; fully Ni-silicided metal gates; simultaneous silicidation; Doping; FinFETs; Germanium silicon alloys; Implants; Instruments; Microelectronics; Silicidation; Silicon germanium; Snow; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469266

Filename

1469266