Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

Author

Fukui, H. ; Hamaguchi, M. ; Yoshimura, H. ; Oyamatsu, H. ; Matsuoka, F. ; Noguchi, T. ; Hirao, T. ; Abe, H. ; Onoda, S. ; Yamakawa, T. ; Wakasa, T. ; Kamiya, T.

Author_Institution

Dept. of Adv. Logic Technol., Toshiba Corp., Kanagawa, Japan

fYear

2005

fDate

14-16 June 2005

Firstpage

222

Lastpage

223

Abstract

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.

Keywords

CMOS integrated circuits; CMOS logic circuits; integrated circuit layout; integrated circuit testing; nanotechnology; 65 nm; CMOS latch circuits; accelerated soft error testing; layout dependence; proton beam; scaling trend; soft-error rate dependence; CMOS logic circuits; CMOS technology; Capacitance; Large scale integration; Latches; Life estimation; Logic testing; Neutrons; Particle beams; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469276

Filename

1469276