Title :
The circuits and physical design of the synergistic processor element of a CELL processor
Author :
Takahashi, O. ; Cook, R. ; Cottier, S. ; Dhong, S.H. ; Flachs, B. ; Hirairi, K. ; Kawasumi, A. ; Murakami, H. ; Noro, H. ; Oh, H. ; Onishi, S. ; Pille, J. ; Silberman, J. ; Yong, S.
Author_Institution :
IBM Syst. & Technol. Group, Austin, TX, USA
Abstract :
A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm2 using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56°C.
Keywords :
CMOS logic circuits; VLSI; logic design; logic gates; microprocessor chips; silicon-on-insulator; 1.4 V; 32 bit; 32b 4-way SIMD; 56 C; 90 nm; CELL processor; CMOS static gates; ISA; SOI technology; VLSI; dynamic circuits; microarchitecture; multi core processor; non-SRAM area; synergistic processor element; CMOS logic circuits; CMOS technology; Clocks; Frequency; Ground penetrating radar; Latches; Logic arrays; Random access memory; Timing; Very large scale integration;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469324
