A DLL-based frequency multiplier for MBOA-UWB system

Author

Lee, Tai-Cheng ; Hsiao, Keng-Jan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2005

fDate

16-18 June 2005

Firstpage

42

Lastpage

45

Abstract

A delay-locked loop (DLL)-based frequency multiplier is designed for the ultrawideband (UWB) mode-1 system. This clock generator with 528-MHz input reference frequency can achieve less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. The UWB clock generator has been fabricated in a 0.18-μm CMOS process and consumes only 54 mW from a 1.8-V supply while exhibiting a sideband magnitude of -35.3 dB and -94 dBc/Hz phase noise at the frequency offset of 50 kHz.

Keywords

CMOS analogue integrated circuits; OFDM modulation; delay lock loops; frequency multipliers; integrated circuit design; signal generators; ultra wideband communication; 0.18 micron; 1.8 V; 50 kHz; 54 mW; CMOS analogue integrated circuits; MBOA-UWB system; OFDM modulation; UWB clock generator; delay-locked loops; fast-settling architecture; frequency multiplier; frequency multipliers; integrated circuit design; signal generators; ultra wideband communication; ultrawideband mode-1 system; wide loop bandwidth; Amplitude modulation; Bandwidth; Circuits; Clocks; Delay; Design engineering; Frequency locked loops; Phase frequency detector; Phase locked loops; Phase noise;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469329

Filename

1469329