Title :
An area-efficient PLL architecture in 90-nm CMOS
Author_Institution :
Nvidia Corp., Santa Clara, CA, USA
Abstract :
An area-efficient phase-locked loop (PLL) design is presented. The PLL architecture allows the implementation of a charge-pump based PLL stabilization filter network using sample-reset techniques and a total loop-capacitor equivalent to a typical ripple-reduction capacitor. Implemented in a logic 90-nm CMOS process, this PLL integrates a total loop capacitance of 3 pF using parasitic metal-metal capacitor structures, measures 160 × 171 μm and exhibits a measured rms period jitter of 1.68 ps at 2.5 GHz.
Keywords :
CMOS digital integrated circuits; active filters; circuit stability; integrated circuit design; integrated circuit metallisation; nanoelectronics; phase locked loops; 1.68 ps; 2.5 GHz; 3 pF; 90 nm; CMOS digital integrated circuits; PLL stabilization filter network; active filters; area-efficient PLL architecture; charge-pumps; circuit stability; integrated circuit design; integrated circuit metallisation; nanoelectronics; parasitic metal-metal capacitor structures; phase-locked loops; ripple-reduction capacitor; sample-reset techniques; total loop-capacitor; CMOS process; Capacitance measurement; Capacitors; Charge pumps; Clocks; Filters; Integrated circuit measurements; Parasitic capacitance; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469330
