Title :
A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC
Author :
Ni, Weining ; Dai, Foster F. ; Shi, Yin ; Jaeger, Richard C.
Author_Institution :
Inst. of Semicond., Chinese Acad. of Sci., China
Abstract :
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q2 random walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35μm CMOS technology with core area of 1.11 mm2.
Keywords :
CMOS digital integrated circuits; circuit tuning; digital-analogue conversion; direct digital synthesis; interpolation; phase noise; 0.35 micron; CMOS technology; DDFS; ROM size; SFDR; current-steering DAC; delta-sigma interpolator; direct digital frequency synthesizer; phase truncation error; random walk switching scheme; spurious-free dynamic range; CMOS technology; Finite wordlength effects; Frequency synthesizers; Noise reduction; Phase locked loops; Phase noise; Quantization; Read only memory; Signal to noise ratio; Table lookup;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469333
