DocumentCode
3549931
Title
Design and analysis of a 20-GHz clock multiplication unit in 0.18-μm CMOS technology
Author
Lee, Jri ; Wu, Shanghann
Author_Institution
Nat. Taiwan Univ., Taipei, Taiwan
fYear
2005
fDate
16-18 June 2005
Firstpage
140
Lastpage
143
Abstract
A 20-GHz clock multiplication unit for SONET OC-768 systems employs dual loops and third-order loop filter to suppress the jitter. Realized in 0.18-μm CMOS technology, this circuit achieves an output jitter of 0.2 ps,rms and 4.5 ps,pp while consuming 40 mW from a 1.8-V supply.
Keywords
CMOS integrated circuits; SONET; clocks; jitter; multiplexing equipment; 1.8 V; 20 GHz; 40 mW; CMOS technology; SONET OC-768 system; clock multiplication unit analysis; clock multiplication unit design; dual loop; jitter suppression; third-order loop filter; CMOS technology; Circuits; Clocks; Frequency conversion; Frequency locked loops; Jitter; Optical filters; Phase detection; Phase frequency detector; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469352
Filename
1469352
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