DocumentCode :
3549932
Title :
A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13μm CMOS
Author :
Kim, Jaeha ; Kim, Jeong-Kyoum ; Lee, Bong-Joon ; Kim, Namhoon ; Jeong, Deog-Kyoon ; Kim, Wonchan
Author_Institution :
Seoul Nat. Univ., South Korea
fYear :
2005
fDate :
16-18 June 2005
Firstpage :
144
Lastpage :
147
Abstract :
A 20GHz phase-locked loop with 4.9pspp/0.65psrms jitter and -101.2dBc/Hz phase noise at 1MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-gm oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than a flip-flop based divider and achieve near 2:1 frequency range. The PLL fabricated in 0.13μm CMOS operates from 17.6GHz to 19.4GHz and dissipates 480mW.
Keywords :
CMOS integrated circuits; flip-flops; frequency dividers; microstrip resonators; phase locked loops; resistors; transmitters; voltage-controlled oscillators; 0.13 micron; 17.6 to 19.4 GHz; 20 GHz; 40 Gbit/s; 480 mW; CMOS; PLL; VCO optimization; coupled microstrip resonator; design iteration procedure; feedforward loop filter; jitter; negative-gm oscillator; phase noise; phase-locked loop; pulsed latch; reference spur suppression; resistor; serializing transmitter; static frequency divider; Frequency conversion; Inverters; Jitter; Oscillators; Phase locked loops; Phase noise; Resistors; Resonator filters; Switches; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
Type :
conf
DOI :
10.1109/VLSIC.2005.1469353
Filename :
1469353
Link To Document :
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