A low leakage SRAM macro with replica cell biasing scheme

The growth of mobile equipment market is spurring demand for low-power SRAM macros. For mobile applications, in particular, there is a need to reduce standby current leakage while keeping memory cell data. For this purpose, several techniques have been reported. They introduce reduction of cell bias voltage in standby state, but the cell bias level is determined by Vth and supply voltage as described later. In 90nm technology and beyond, fluctuation of Vth is increasing and leakage reduction efficiency of these techniques is greatly affected. Therefore, a cell leakage reduction technique immune to process and/or environment fluctuations is required. In addition, leakage reduction in row decoder circuit is also desirable, because standby current leakage in peripheral circuits is dominated by row decoders. In order to meet these requirements, a novel cell bias control technique and a novel row decoder circuit are proposed. We fabricated a 90nm 512Kb low leakage SRAM macro.