A 3.125-Gb/s sub-milliwatt CMOS signal detector circuit

This paper describes a 3.125-Gb/s signal detector circuit that activates a powered-down receiver on the arrival of incoming data. The signal detector operates at a clock speed lower than the incoming data rate to lower the power dissipation in stand-by mode. It uses a frequency-modulated clock generator, asynchronous to the data, alleviating the need for the recovered clock and allowing the receiver to remain in the low-power mode. The circuit is fabricated in a 0.15-μm CMOS technology over an area of 39 μm × 95 μm. The power dissipation is 700 μW.