Title :
Galois field computation LSI: a reconfigurable chip for high-speed communication
Author :
Endou, Nobuharu ; Kasai, Yuji ; Iwata, Masaya ; Takahashi, Eiichi ; Higuchi, Tetsuya
Author_Institution :
Assoc. of Super-Adv. Electron. Technol., MIRAI, Tsukuba, Japan
Abstract :
A new reconfigurable LSI for Galois field computation has been developed, implementing high-speed operation while maintaining general FPGA versatility. Customized for high-speed communication applications, the chip bridges the performance gap between custom LSIs and FPGAs. Including two types of building blocks optimally designed for Galois field computation, performance of the chip is 2 to 10 times faster than for FPGAs, providing parallel data transmission for on-board and back-plane connections (2Gbps on each 70cm-line).
Keywords :
Galois fields; Reed-Solomon codes; cyclic redundancy check codes; data communication equipment; field programmable gate arrays; flip-flops; large scale integration; reconfigurable architectures; 2 Gbit/s; 70 cm; 81 micron; 96 micron; CRC; FPGA; Galois field computation; PN generation; Reed-Solomon decoder; adaptive input-output; cyclic redundancy code; field programmable gate array; high-speed communication; large scale integration; parallel data transmission; reconfigurable chip; Circuits; Convolution; Convolutional codes; Cyclic redundancy check; Decoding; Field programmable gate arrays; Galois fields; Large scale integration; Multiaccess communication; Reed-Solomon codes;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469368
