DocumentCode :
3549949
Title :
A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application
Author :
Murachi, Yuichiro ; Matsuno, Tetsuro ; Hamano, Koji ; Miyakoshi, Junichi ; Miyama, Masayuki ; Yoshimoto, Masahiko
Author_Institution :
Fac. of Eng., Kanazawa Univ., Ishikawa, Japan
fYear :
2005
fDate :
16-18 June 2005
Firstpage :
212
Lastpage :
215
Abstract :
This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high resolution video application like an HD camcorder. It features a novel hierarchical algorithm and a low power ring-connected systolic array architecture. It supports the frame/field and bi-directional prediction with half-pel precision for 1920×1080@30fps resolution video. The search range is ±128×±64. The ME core integrates 2.25M transistors in 3.1mm×3.1mm using 0.18micron technology.
Keywords :
low-power electronics; microprocessor chips; motion estimation; systolic arrays; video signal processing; 0.18 micron; 3.1 mm; 95 mW; HDTV; MPEG2; hierarchical algorithm; high resolution video; low power; motion estimation; processor core; systolic array architecture; Bidirectional control; Energy consumption; HDTV; High definition video; Motion estimation; Power engineering and energy; Search methods; Systolic arrays; TV; Video equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
Type :
conf
DOI :
10.1109/VLSIC.2005.1469369
Filename :
1469369
Link To Document :
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