An image filtering processor for face/object recognition using merged/mixed analog-digital architecture

Author

Korekado, Keisuke ; Morie, Takashi ; Nomura, Osamu ; Nakano, Teppei ; Matsugu, Masakazu ; Iwata, Atsushi

Author_Institution

Graduate Sch. of Life Sci. & Syst. Eng., Kyushu Inst. of Technol., Kitakyushu, Japan

fYear

2005

fDate

16-18 June 2005

Firstpage

220

Lastpage

223

Abstract

This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 μm CMOS performs 6-bit precision convolutions for an image of 80×80 pixels with a kernel size of up to 51×51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

Keywords

CMOS integrated circuits; face recognition; image processing; large scale integration; low-power electronics; microprocessor chips; mixed analogue-digital integrated circuits; object recognition; pulse width modulation; 0.35 micron; 280 mW; 6 bit; 8.2 ms; CMOS; SPICE simulation; convolution-kernel size; convolutional neural networks; digital circuits; face recognition; image filtering processor core; large-scale integration; mixed analog-digital architecture; object recognition; power consumption; pulse-width modulation; Analog-digital conversion; Digital circuits; Digital modulation; Filtering; Large scale integration; Object recognition; Pixel; Pulse circuits; Pulse width modulation; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469371

Filename

1469371