Notice of Violation of IEEE Publication PrinciplesA -86dBc reference spurs 1-5GHz 0.13μm CMOS PLL using a dual-path sampled loop filter architecture

Notice of Violation of IEEE Publication Principles

"A -86dBc reference spurs 1-5GHz 0.13 μm CMOS PLL using a dual-path sampled loop filter architecture"
by Maxim, A.
in the Proceedings of the 2005 Symposium on VLSI Circuits, Digest of Technical Papers.
16-18 June 2005 Page(s):248 - 251

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A CMOS PLL was realized using a dual-path sampled loop filter, which reduces the reference spurs down to the -86dBc. Both the integral and proportional loop filter paths use a sampled configuration that completely isolates the oscillator from the switching effects of the charge-pumps, minimizing thus the ripple on the oscillator control signal. The 300×750 μm² PLL was fabricated in a 0.13μm CMOS process having a 1-5GHz frequency range, 5-12MHz channel separation, -86dBc reference spurs, <0.5% T_osc RMS jitter, and draws <100mW from a 2.5V supply.