DocumentCode
3549962
Title
Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques for 2-3GHz on-chip cache arrays in microprocessors on 90nm logic technology
Author
Khellah, Muhammad ; Ye, Yibin ; Somasekhar, Dinesh ; Casper, Derek ; Bloechel, Bradley ; Nguyen, Trang ; Dermer, Greg ; Zhang, Kevin ; Pandya, Gunjan ; Farhang, Ali ; De, Vivek
Author_Institution
Circuits Res., Intel, Hillsboro, OR, USA
fYear
2005
fDate
16-18 June 2005
Firstpage
262
Lastpage
263
Abstract
Bitline leakage compensation (BLC) and leakage reduction (BLR) techniques, implemented for cache arrays on a testchip in a 90nm logic technology, demonstrate improvement in operational frequency from 1.2GHz to 2GHz for BLC, and to 3GHz for BLR, with 17% and 10% area impacts, respectively.
Keywords
cache storage; integrated circuit measurement; logic testing; microprocessor chips; 1.2 to 3 GHz; 90 nm; bitline leakage compensation; bitline leakage reduction; logic technology; microprocessors; on chip cache arrays; Calibration; Circuit testing; Delay; Frequency; Logic arrays; Logic circuits; Logic design; Logic testing; Microprocessors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469381
Filename
1469381
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