A 1.88ns 54×54-bit multiplier in 0.18μm CMOS based on multiple-valued differential-pair circuitry

Author

Mochizuki, Akira ; Hanyu, Takahiro

Author_Institution

Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan

fYear

2005

fDate

16-18 June 2005

Firstpage

264

Lastpage

267

Abstract

This paper presents a new 54 × 54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multilevel current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm² die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

Keywords

CMOS logic circuits; current-mode logic; digital arithmetic; multiplying circuits; multivalued logic circuits; 0.18 micron; 1.8 V; 54 bit; 74.2 mW; CMOS integrated circuit; conditional sum adder; critical path delay; crosstalk noise reduction; current driving; current mode linear summation; current-mode logic; multiple-valued differential-pair circuitry; multiplier; signed-digit number; Adders; CMOS technology; Circuit noise; Crosstalk; Delay; Digital signal processing; Graphics; Logic; Reduced instruction set computing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469382

Filename

1469382