Title :
Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits
Author :
Kosaka, Daisuke ; Nagata, Makoto ; Hiraoka, Yukio ; Imanishi, Ikuo ; Maeda, Masakatsu ; Murasaka, Yoshitaka ; Iwata, Atsushi
Author_Institution :
Dept. of Comput. & Syst. Eng., Kobe Univ., Japan
Abstract :
A deep n-well guard-ring, DNW-GR, provides effective isolation from substrate-coupled high frequency noises in combination with high-resistive p-type substrates. AC-measurements of S21 with port geometry and guard-ring structure dependencies are reported in a 0.25-μm CMOS standard mixed-signal technology with p-type substrates having the bulk resistivity from 10 Ωcm to 3 kΩcm. It is shown that DNW-GR on a 1-kΩcm substrate gains 20dB improvement in isolation against 1-GHz coupling, compared with a p+ guard-ring on a standard 10-Ωcm substrate. S21 simulations with substrate equivalent circuit models derived by way of F-matrix computation on test structures are in good agreement with measurements for a frequency range over 5 GHz. The substrate models can compactly as well as precisely include layout-level isolation effects in circuit simulations for a mixed-signal/RF design.
Keywords :
CMOS integrated circuits; S-parameters; circuit simulation; equivalent circuits; integrated circuit design; isolation technology; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; 0.25 micron; CMOS mixed signal circuits; F-matrix computation; RF circuits; S21; bulk resistivity; circuit simulations; deep n-well guard ring; equivalent circuit models; isolation strategy; substrate coupling; CMOS technology; Circuit noise; Circuit simulation; Circuit testing; Computational modeling; Conductivity; Coupling circuits; Geometry; Isolation technology; Radio frequency;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469385