The cross charge-control flip-flop: a low-power and high-speed flip-flop suitable for mobile application SoCs

Author

Hirata, Akio ; Nakanishi, Kazuyuki ; Nozoe, Mitsushi ; Miyoshi, Akira

Author_Institution

Syst. LSI Dev. Div., Matsushita Electr. Ind. Co., Nagaokakyo, Japan

fYear

2005

fDate

16-18 June 2005

Firstpage

306

Lastpage

307

Abstract

This paper presents a low power and high-speed flip-flop named cross charge-control flip-flop (XCFF). It has two dynamic nodes driving output transistors separately. The minimum power-delay product of the XCFF is 48% smaller than that of CMOS flip-flop and 20% smaller than that of the semi-dynamic flip-flop (SDFF). Applying it to a 125-MHz microprocessor core, we can achieve 10% power reduction without any speed or area penalty.

Keywords

flip-flops; high-speed integrated circuits; low-power electronics; microprocessor chips; system-on-chip; 125 MHz; cross charge-control flip-flop; high-speed flip-flop; low-power flip flop; microprocessor core; mobile application SoC; system on chip; Capacitance; Circuit simulation; Clocks; Delay effects; Flip-flops; Latches; MOSFETs; Microprocessors; Power dissipation; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469392

Filename

1469392

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549974