Title :
A 14bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40MS/s
Author :
Matsui, Hirofumi ; Ueda, Masaya ; Daito, Mutsuo ; Iizuka, Kunihiko
Author_Institution :
Devices Technol. Res. Labs., SHARP, Nara, Japan
Abstract :
A 14bit digitally self-calibrated pipelined ADC featuring the adaptive bias optimization is fabricated in a 0.18μm dual-gate CMOS and consumes 19.2, 33.7, 50.5 and 72.8mW respectively when operating at 10, 20, 30 and 40MS/s. In all the operating speeds with temperature variation up to 80°C, DNL is kept between ±0.60LSB. When operating at 20MS/s, it achieves 73.2dB SNR and 70.4dB SNDR.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; pipeline arithmetic; 0.18 micron; 14 bit; 19.2 mW; 33.7 mW; 50.5 mW; 72.88 mW; adaptive bias optimization; arbitrary speed; bias current optimization; digital calibration; digitally self-calibrated pipelined ADC; dual-gate CMOS; temperature variation; Analog circuits; CMOS technology; Calibration; Consumer electronics; Fluctuations; Laboratories; Optimization methods; Power dissipation; Temperature; Transfer functions;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469398
