DocumentCode
3549987
Title
An 8 Mbit DRAM design using a 1 Tbulk cell
Author
Malinge, Pierre ; Candelier, Philippe ; Jacquet, François ; Martin, Sophie ; Ranica, Rossella ; Villaret, Alexandre ; Mazoyer, Pascale ; Fournel, Richard ; Allard, Bruno
Author_Institution
CR&D, STMicroelectron., Crolles, France
fYear
2005
fDate
16-18 June 2005
Firstpage
358
Lastpage
361
Abstract
An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 μA. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.
Keywords
CMOS memory circuits; DRAM chips; integrated circuit design; 10 ns; 8 Mbit; DRAM design; bit fail rate; bulk substrate; common mode reference current; current read margin; current sense-amplifier; data retention; eDRAM memory cell; floating body one transistor cell; memory chip; CMOS logic circuits; Costs; Current measurement; Logic devices; Memory architecture; Random access memory; Read-write memory; Silicon on insulator technology; Voltage; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469404
Filename
1469404
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