• DocumentCode
    3549988
  • Title

    A 0.4-V high-speed, long-retention-time DRAM array with 12-F2 twin cell

  • Author

    Takemura, Riichiro ; Itoh, Kiyoo ; Sekiguchi, Tomonori ; Akiyama, Satoru ; Hanzawa, Satoru ; Kajigaya, Kazuhiko ; Kawahara, Takayuki

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo, Japan
  • fYear
    2005
  • fDate
    16-18 June 2005
  • Firstpage
    362
  • Lastpage
    365
  • Abstract
    We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operation. The write time and retention time of the twin-cell array become shorter by 50% and longer by more than 20% than those of a single cell array, enabling a 0.4-V operation. Furthermore, the cell accepts the plate-driven scheme without dummy cell, lowering the necessary word-line voltage by 0.4 V.
  • Keywords
    DRAM chips; cellular arrays; integrated circuit design; low-power electronics; 0.4 V; 12-F2 twin cell; dummy cell; low voltage RAM; plate-driven cell; retention time; twin-cell DRAM array; word line voltage; write time; Capacitance measurement; Circuits; Noise figure; P-n junctions; Random access memory; Tellurium; Time measurement; Very large scale integration; Virtual colonoscopy; Voltage measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
  • Print_ISBN
    4-900784-01-X
  • Type

    conf

  • DOI
    10.1109/VLSIC.2005.1469405
  • Filename
    1469405
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549988