Title :
A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C10 minimization and self-calibration techniques
Author :
Park, Churoo ; Chung, Hoeju ; Lee, Yun-Sang ; Kim, Jae-Kwan ; Lee, Jae-Jun ; Chae, Moo-Sung ; Jung, Dae-Hee ; Choi, Sung-Ho ; Seo, Seung-Young ; Park, Taek-Seon ; Shin, Jun-Ho ; Cho, Jin-Hyung ; Lee, Seunghoon ; Kim, Kyu-hyoun ; Lee, Jung-Bae ; Kim, Chang
Author_Institution :
DRAM Design, Samsung Electron. Co., Hwasung, South Korea
Abstract :
A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in 80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD protection, rendering C10 minimization for the enhanced signal integrity in point-to-2points interfacing. Hybrid latency control scheme is proposed to achieve higher bandwidth as well as to efficiently turn DLL on and off. Temperature readout and per-bank-refresh is also implemented.
Keywords :
CMOS memory circuits; DRAM chips; integrated circuit design; minimisation; 1.5 V; 1.6 Gbit/s; 512 Mbit; 80 nm; C10 minimization; DDR3 synchronous DRAM prototype; DLL switch; SCR type ESD protection; enhanced signal integrity; hybrid latency control; output drivers; per-bank-refresh; point-to-2points interfacing; self calibration techniques; temperature readout; Automata; Bandwidth; Calibration; Clocks; Control systems; Delay; Prototypes; SDRAM; Temperature control; Voltage control;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469407
