Title :
A quad 3.125 Gbps transceiver cell with all-digital data recovery circuits
Author :
Lee, Bong-Joon ; Hwang, Moon-Sang ; Kim, Jaeha ; Jeong, Deog-Kyoon ; Kim, Wonchan
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
This paper describes a quad 3.125 Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase-averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1 UI. Implemented in 0.13 CMOS, the transceiver tolerates up to 0.67 UI of total jitter at 3.125Gbps.
Keywords :
CMOS digital integrated circuits; digital communication; jitter; transceivers; 3.125 Gbit/s; CMOS integrated circuit; all-digital data recovery circuit; internal forward path; jitter tolerance; on-chip JTOL measurement circuits; phase-averaging method; quad transceiver; Circuits; Clocks; Degradation; Delay; Fluctuations; Jitter; Latches; Phase locked loops; Quantization; Transceivers;
Conference_Titel :
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN :
4-900784-01-X
DOI :
10.1109/VLSIC.2005.1469410
