An 8-bit resolution, 12-bit accuracy, 500 MS/s update rate, sub-pV.s glitch energy CMOS D/A converter

A DAC with 8-bit of resolution, and 12-bit of intrinsic accuracy, integrated in a standard digital 0.5 µm CMOS technology is presented. The DAC is based on a coarse-fine doubly-segmented 6+2 current steering architecture. The overall symmetry of the architecture combined with the synchronization of all blocks allows to reach a glitch energy of about one pVċs. By adjusting the voltage supply of the latches it is possible to improve the timing and the crossing point of the switching control signals, so that the glitch energy specification is reduced to sub-pVċs values. To obtain an update rate of 500 MS/s a fast two-stage row-column decoding logic is used.