DocumentCode :
3551508
Title :
A developmental intrinsic-barrier transistor
Author :
Hittinger, W.C. ; Warner, R.M.
Volume :
1
fYear :
1955
fDate :
1955
Firstpage :
13
Lastpage :
13
Abstract :
The intrinsic-barrier design extends transistor frequency range without sacrificing power-handling capacity. A review of the design principles is presented, together with a description of a moderate-power developmental model, the M1830. A set of 155 M1830 units was recently made in the laboratory; 53 of these possessed measurable VHF characteristics, and diagrams are presented here showing parameter distributions for these units. Output power determinations were made for 15 units (not necessarily the best ones of the group). Nine units gave more than 20 milliwatts of sustained useful output at 200 megacycles per second. The best unit studied in detail thus far displayed an alpha of 0.88 at 100 cycles per second, ohmic base resistance of 106 ohms at 250 megacycles per second, collector capacitance of 0.2 micromicrofarads, grounded base cutoff frequency of 238 megacycles per second, and output power of 30 milliwatts at 200 megacycles per second.
Keywords :
Capacitance; Cutoff frequency; Laboratories; Power generation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1955 International
Type :
conf
DOI :
10.1109/IEDM.1955.186919
Filename :
1471966
Link To Document :
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