Hermetically sealed silicon chip diodes and transistors

Modern computer design has created a demand for large quantities of high speed logic diodes and transistors. To be technically and economically feasible extreme reliability must be combined with high performance at the lowest possible cost. The glass sealed planar devices described in this paper were designed to fill these specific requirements. The need for a costly header was eliminated by hermetically sealing each device with a thin glass film. A single sided structure was chosen to simplify interconnection problems. Fabricating terminals, as an integral part of the chip structure, permits interconnection with a high degree of flexibility and eliminates the need for thermocompression bonding. Surface passivation with silicon dioxide and difficulties of glass application are discussed in conjunction with the problems of ohmic contracts to P and N silicon, contact lands over passivated junctions, capacitance of contact lands, and hermetic glass-to-metal seals. Performing all fabrication steps on wafers having mass arrays of devices permits a significant reduction in device cost. Processes and photoengraving techniques for making the devices are described. Data on the electrical and life test performance is presented and evaluated.