A high-speed, medium-power silicon planar epitaxial switching transistor

To take full advantage of new developments in solid-state memory technology, driver transistors with greatly reduced switching transient times are needed, while still maintaining existing voltage and current capabilities. This paper describes the development of a transistor with just such properties. It is a double-diffused, epitaxial, silicon NPN planar structure employing a unique impurity gradient in the epitaxial layer. Since the switching transient time in a common emitter configuration is essentially the base charge, QB, plus the collector charge, QC, divided by the base drive current Ib, the design of such a transistor involves the optimization of QBand Qcat the desired switching current capability. Since Qcin general increases linearly with collector junction area and is relatively insensitive to collector current, this would indicate that a small size is desirable. On the other hand, QBin general increases non-linearly with a decrease in collector junction area; thus a large size is desirable. Since these effects are mutually incompatible, a compromise has to be reached. The result is a transistor with a BVCBO> 80 v., a BVCEO> 30 v., that will switch 1 ampere through a 25 volt collector voltage swing in 8 nsec. or less, 10 to 90%, with a 100 ma. base drive. With increased base drive, 400 ma., the switch time can be reduced to 2 nsec. VBE(SAT)is less than 1.5 v. and VCE(SAT)is less than 1.0 v.