The design of a 1 Gc multi-channel field-effect transistor theory and experiment

A plane parallel analog transistor has been fabricated by combining the techniques of epitaxial growth, impurity diffusion and diffusion masking as presently used in planar silicon device and integrated circuit fabrication. The MULTI-CHANNEL FET is an exact solid state equivalent of a closely spaced vacuum tube triode. The gate or grid of this unipolar device is completely embedded inside the semiconductor. It consists of a high density mesh network, which achieves a high transconductance and allows for high saturation currents. The MULTI-CHANNEL FET is readily adaptable to integrated circuit techniques in its planar form and extends transconductance, frequency of operation and power output beyond that of standard field effect transistor designs. There will be a discussion of several device structures fabricated during this study. Experimental devices with 100 parallel-channels achieved the following electrical characteristics: gm= 10mA/V, IDSS= 25mA, VP= 10V, CGD= 5 pf (at 10V), BVDSS= 60V, IGS= 10nA (at 10V), PG = 14 db at 60 Mc, PG = 10 db at 100 Mc, extrapolated fmax= 300 Mc and a 3 db gmcut-off frequency of 275 Mc. A device capable of producing a maximum frequency of oscillation of 1,000 Mc in relation to optimum geometry and impurity profiles will be presented.