Title :
A method of delay fault test generation
Author :
Glover, C. Thomas ; Mercer, M. Ray
Author_Institution :
Dept. of Electr. & Comput. Eng., Austin Univ., TX, USA
Abstract :
The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input. The authors extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at-tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.<>
Keywords :
automatic test equipment; logic testing; automatic test generation; binary decision diagram; delay fault test generation; fully transitional path; graphs representing stuck-at-tests; robust delay fault coverage; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Computer simulation; Costs; Fault detection; Latches; Propagation delay;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14740