A novel oxide isolation process

A technique is described for preparing oxide isolated silicon structures suitable for integrated circuit applications. The key step in this new process is the use of a silicon carbide stopping layer that is vapor deposited prior to the growth of the silicon dioxide dielectric layer. This silicon carbide layer substitutes a simple single crystal removal step for a very critical removal step that is common to most oxide isolation processes. The fact that silicon carbide has a greater hardness than either silicon or silicon dioxide makes it an excellent material for use in oxide isolated integrated circuits. Silicon wafers of up to 1.3" in diameter can be produced with single crystal isolated structures that are uniform in thickness across the entire wafer. The application of this new isolation technique to several integrated circuit applications will be detailed and some performance characteristics will be presented.