A high-performance lateral geometry transistor for complementary integrated circuits

The lateral transistor has been shown to be highly useful in the realization of low-frequency circuits. This simple structure has been limited essentially to DC applications, however, by bandwidth and switching time performance. The PNP device to be described in this paper overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk portion of the E-B junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried n+ layer such that injection of carriers greater than a diffusion length from the collector is minimized. In addition to the reduction of , a further consequence of the n+ region is the introduction of a graded-base region such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an ftof 10 to 15 MHz at collector currents of 0.25 ma and rise, fall, and storage times of the order of tens of nanoseconds.