A modified lateral PNP transistor for integrated complementary circuits

A modified lateral transistor structure involving the intersection of the diffused p+ emitter profile with an underlying n+ layer yielded devices which showed an improvement in performance with respect to a simple lateral transistor structure. It was possible to prepare devices with a d.c. current gain of 50, a cutoff frequency ftof 50 MHz and switching characteristics with an trof 15 nanoseconds, a tsof 60 nanoseconds and a tfof 45 nanoseconds. Certain device characteristics are limited by the geometry and minority carrier lifetime as well as by their structure. Design considerations for a complementary pair of a lateral p-n-p transistor and a conventional bi-polar n-p-n transistor are discussed, hFE, ft, junction capacitances, breakdown voltages, saturation voltages and switching characteristics are analyzed in terms of device geometry, minority carrier lifetime, photolithographic tolerance, diffusion profile and epitaxial growth control during the processing of the device.